The ability to dope polysilicon gates to different degrees allows for adjustment of the work function of gate electrode materials to particular types of metal oxide silicon (MOS) transistors. However, it is now understood that polysilicon gates can accommodate only a finite amount of dopants due to the depletion of gate charge carriers at the interface between the gate and gate dielectric, when the gate is biased to invert the channel.
In view of the limitations of doped polysilicon, metal gates have been proposed as an alternative to polysilicon because they have a much larger supply of charge carriers than doped polysilicon gates. One accepted way of manufacturing metal gates is to use a gate last process where the gate is formed after the high thermal budgets have been done to activate the source/drain dopants. In such processes, a polysilicon gate is first formed. A source/drain extension (for example, lightly doped drain (LDD)) is formed, followed by the formation of a spacer, which is used to offset the deep source/drain an appropriate distance from the gate. The polysilicon gate is then removed from between the sidewall spacers and the appropriate metal is then deposited between the sidewall spacers to form the metal gate electrode.